1. Field of the Invention
This invention relates to magnetic random access memory devices and, more particularly, to magnetic random access memory architectures.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
Recently, advancements in the use of magnetoresistive materials have progressed the development of magnetic random access memory (SAM) devices to function as viable non-volatile memory circuits. In general, MRAM circuits exploit the electromagnetic properties of magnetoresistive materials to set and maintain information stored within individual magnetic memory cell junctions or elements of the circuit. In particular, MRAM circuits utilize magnetization direction to store information within a magnetic junction, and differential resistance measurements to read information from the magnetic junction. In general, an MRAM circuit includes one or more conductive lines with which to generate magnetic fields such that the magnetization directions of one or more magnetic junctions of the MRAM circuit may be set. Typically, the conductive lines are arranged in series of columns and rows having magnetic junctions interposed at the overlap points of the conductive lines. In this manner, the circuit may include a plurality of memory cells arranged within an array. In some cases, the conductive lines may be referred to as “bit” and “digit” lines. In general, “bit” lines may refer to conductive lines that are used for both read and write operations of the magnetic junction. In most cases, the bit lines are arranged in contact with the magnetic junctions. “Digit” lines, on the other hand, may refer to the conductive lines spaced vertically adjacent to the magnetic junctions and used primarily during write operations of the array.
In general, an individual magnetic junction can be written to by applying current simultaneously along a bit line and a digit line corresponding to the particular magnetic junction. Such an individual magnetic junction may herein be referred to as a selected magnetic junction, or the magnetic junction intentionally targeted for a writing procedure. During the writing procedure, however, the multitude of other magnetic junctions arranged vertically adjacent to the bit line and the digit line corresponding to the selected junction will also sense current. Such magnetic junctions are herein referred to as half-selected junctions or disturbed junctions, since a magnetic field is induced about them from the bit or digit line used to program the selected magnetic junction. Even though a less effective magnetic field is applied to these disturbed cells, variations within magnetic junctions may allow a magnetic field induced by one current carrying line to switch the magnetization directions of one or more of the disturbed cells. In addition, variations within magnetic cell junctions may cause switching of magnetization directions to vary relative to pulse width and timing of current applications along the bit and digit lines. As a result, a false bit may, in some embodiments, be inadvertently written to one or more of the disturbed cells during a write operation of the array, reducing the reliability of the device.
Due to the random incidence and magnitude of magnetic cell junction variations, the distribution of current needed to program a selected cell without programming disturbed cells may vary from cell to cell as well as die to die and wafer to wafer. As a result, determining a program switching distribution for an array may, in some embodiments, be difficult. In some embodiments, the temperature of magnetic cell junctions and/or the direction along which current is applied to a bit line may affect the amplitude, pulse width and/or timing needed to induce a change in magnetization states within magnetic cell junctions, making the determination of a program switching distribution more complicated. In some cases, process parameters and design specifications of device may be specifically configured to accommodate a program switching distribution arbitrarily set for the device. In this manner, reliability of the device may not depend on determining a program switching distribution. However, accommodating a specific program switching distribution typically results in process parameters and design specifications having tight tolerances, which may not be easily obtained in some embodiments. As a result, production yield may be undesirably low and manufacturing costs may be unreasonably high.
During a read operation of an MRAM array, data may be read from a magnetic cell junction by creating a current path from a corresponding bit line through the magnetic cell junction to an underlying transistor such that a resistance measurement may be obtained. The underlying transistor may be turned “on” by the application of a bias voltage. In general, the resistance measured through a magnetic cell junction may be a function of the applied bias voltage. Variations within magnetic cell junctions may, however, cause the level of bias voltage attributed to a maximum sense signal to vary from cell to cell as well as from die to die and wafer to wafer. Consequently, the determination of an optimum bias voltage may be difficult in some embodiments. In addition, variations within magnetic cell junctions may cause a breakdown voltage of a magnetic cell junction to be low in some embodiments. Low breakdown voltages may, in some cases, cause read failures, reducing the reliability of the device. In general, a breakdown voltage of a magnetic cell junction may decrease with time. As such, an MRAM array may function properly during testing, but may, in some cases, fail at a later point in time, resulting in unpredictable reliability.
During a read operation of an MRAM array, data may be read from a magnetic cell junction by creating a current path from a corresponding bit line through the magnetic cell junction to an underlying transistor such that a resistance measurement may be obtained. The underlying transistor may be turned “on” by the application of a bias voltage. In general, the resistance measured through a magnetic cell junction may be a function of the applied bias voltage. Variations within magnetic cell junction may, however, cause the level of bias voltage attributed to a maximum sense signal to vary from cell to cell as well as from die to die and wafer to wafer. Consequently, the determination of an optimum bias voltage may be difficult in some embodiments. In addition, variations within magnetic cell junctions may cause a breakdown voltage of a magnetic cell junction to be low in some embodiments. Low breakdown voltages may, in some cases, cause read failures, reducing the reliability of the device. In general, a breakdown voltage of a magnetic cell junction may decrease with time. As such, an MRAM array may function properly during testing, but may, in some cases, fail at a later point in time, resulting in unpredictable reliability.
In order to examine the functionality an MRAM array, various settings of the functional parameters of the array may be tested. In some embodiments, a complementary metal-oxide-semiconductor (CMOS) memory circuit may be configured to provide a variety of settings to an MRAM array. However, since a CMOS memory circuit is volatile, the circuit cannot be used to provide settings for an MRAM array without an available source of settings to load therein. In some cases, the settings may be provided to an MRAM array by fuses and/or metal mask options. Settings within fuses and metal mask options, however, are fixed and, therefore, are generally difficult to provide a variety of settings to an array for testing. For example, fuses can only be blown once and, therefore, cannot be reprogrammed. A vast number of fuses may be coupled to an array to provide a variety of settings, but such an incorporation of fuses may undesirably occupy a large area on the chip and add additional manufacturing steps. In addition, metal mask options cannot be adjusted on a die by die basis.
As noted above, several factors may affect operations of an MRAM array and, in some embodiments, cause read and/or write failures. Failures which are not attributed to such factors, however, may occur within an MRAM array as well. For example, write failures may occur if an inadequate amount of current is supplied to the bit and digit lines. In particular, data may not be correctly programmed within an array if a sufficient amount of current is not applied to the bit and digit lines. Such write failures may occur during power supply failures, reducing the reliability of the device.
Therefore, it would be advantageous to develop an MRAM device which does not allow a write operation to be performed during a power supply failure. In addition, it may be beneficial to provide an MRAM device which is able to change and optimize parameter settings at which the device is operated. Moreover, it would be advantageous to provide methods for identifying magnetic cell junctions which may be susceptible to write and/or read failures. Furthermore, it may be beneficial to develop a magnetic memory array with a means to provide a non-volatile source of functional settings as well as the ability to reprogram such a means.